With development of electronic information technology, low-power design and application of memory products play an important role in electronic systems. A charge pump is a type of switched capacitor voltage converter. Its conversion efficiency is high and its peripheral circuits are simple, therefore it has been widely used in modern power management circuits. The charge pump is suitable for memory, networking equipment and portable applications.
The charge pump is also called a switched capacitor voltage converter, and includes a reference circuit, a comparator circuit, a converter circuit, and a control circuit. A switch array, an oscillator, a logic circuit, and the comparator circuit are configured to rise voltage. A capacitor is configured to store energy. The charge pump may apply a mechanism of pulse-frequency modulation and, only when charges must be transferred out to maintain output regulation, the charges are generated. When the output voltage of the charge pump is higher than the target regulation voltage, the charge pump operates in a standby mode, in which the current consumption is minimal because the charges stored in the output capacitor can provide the load current. With continuous discharge of the output capacitor, the output voltage is gradually reduced to the target regulation voltage and, then, the charge pump can enter an active mode and transfer the charges to the output terminal. The charges are supplied to the load current, and increase the voltage of the output capacitor.
FIG. 1 is a schematic diagram of an existing charge pump voltage regulator. As shown in FIG. 1, the existing charge pump voltage regulator 100 includes a charge pump circuit 101, a resistor voltage divider circuit 102, and a voltage comparator 103. An output terminal of the charge pump circuit 101 is connected to an output terminal of the charge pump voltage regulator 100 and outputs a signal Vout. The resistor voltage divider circuit is suitable to divide the signal Vout and outputs a divided voltage Vdiv. A first input terminal and a second input terminal of the voltage comparator 103 respectively input a reference voltage Vref and the divided voltage Vdiv. The comparison result outputted from the voltage comparator 103 can be configured to control a clock oscillator (not labeled) to output a drive clock signal CLK, to drive the charge pump circuit 101.
Using a memory integrated with the charge pump voltage regulator 100 as an example, the memory can control the charge pump voltage regulator 100 to operate in the standby mode and the active mode. Referring to FIG. 1 and FIG. 2, Vs is a target voltage outputted from the charge pump voltage regulator 100. When the signal Vout is larger than the target voltage Vs, the signal Vout is dropped and the charge pump circuit 101 operates in the standby mode. When the signal Vout is smaller than the target voltage Vs, the signal Vout is raised and the charge pump circuit 101 operates in the active mode. The rise or drop of the signal Vout depends on the comparison result with the reference voltage Vref. The logic level indicated by different comparison results outputted from the voltage comparator 103 is identified by the logic circuit (not labeled), to control the clock oscillator to output the drive clock signal CLK. In the existing charge pump voltage regulator 100, the charge pump circuit 101 is turned on frequently. In addition, the resistor voltage divider circuit 102 is configured to divide the signal Vout, such that, in the standby mode, the current in the output terminal of the charge pump voltage regulator 100 is large.
Therefore, the charge pump voltage regulator 100 formed by existing techniques fires an issue of large standby power consumption. The disclosed device structures and methods are directed to solve one or more problems set forth above and other problems.